The SDA-2 decoder is a high-performance HiFi-class audio decoding amp preamplifier. It uses XMOS's latest xCORE-200 series chip as the USB Audio solution, and uses the AKM497 of the AKM third-generation DAC as the DA conversion chip, AK4118 as a digital audio input receiver chip, uses STM32 as the control of the whole machine, Xilinx's large-scale FPGA as the processing of the clock system and digital audio stream. The amp part adopts 4-way full balance design, independent discrete class A amp drive circuit; the front stage output adopts analog pre-stage design, which is not the way of digital attenuation affecting sound dynamics; has rich input and output interfaces, including standard USB2 .0 input interface, SPDIF coaxial and AES balanced input, analog XLR balanced output, analog RCA output. PCM supports up to 384Khz, DSD uses native direct solution technology, supports up to DSD512, and all interfaces support DSD decoding. The DAC chip adopts AKM's flagship DAC AK4497EQ; the DSD adopts the native direct solution mode. The DSD digital stream does not pass through the internal digital filter and modulator, and works in the NOS mode. The PCM can also choose to work in the NOS mode, which is in line with the HQPlayer design concept. . SDA-2 is the first decoding amp preamp product we developed, mainly using the following four main technologies: 1, USB part uses our first generation isolation technology: SCIT technology (Singxer capacitor isolation technique), SCIT technology is a full isolation technology (ground isolation), high-speed signal using 150Mbps isolation chip, low-speed signal using optocoupler isolation It can completely isolate the interference from the PC; the USB version of the high version can basically reach the level of the SU-1 independent digital interface. 2, source synchronization technology and FPGA shaping technology, re-shaping the isolated I2S signal; thus eliminating the additive jitter caused by the isolation chip; 3, The self-developed clock system uses a femtosecond crystal oscillator as the local reference clock; 4, 4 way class A discrete amp circuit, full balanced amplification of 8 chip transistors per route.

Sample rate supported by each input interface:

PCM: 44.1KHz,48KHz,88.2KHz,96KHz,176.4KHz,192KHz,352.8KHz,384KHz

DSD: 2.8 MHz (DSD64) - DoP,native
5.6 MHz (DSD128) - DoP,native
11.2 MHz (DSD256) - DoP,native
22.5792 MHz (DSD512) - native
Bit width: Up to 32 bit over I2S output
                Up to 24 bit over S/PDIF

Electrical standards for each interface:
1, USB input socket is a standard USB-B type female socket, USB power supply range is 4.5V-5.1V;
2, SPDIF interface input standard S / PDIF signal, input impedance is 75 ohms, AES input impedance is 110 ohms;
3, the power input is 115V/ 230V AC, and the internal 30W O-type transformer is used for power supply;
4, I2S input is LVDS level in the form of HDMI interface, compatible with SU-1 interface;

Analog output performance:
Output level (0dBFS):
      PCM: RCA single-ended output is 2V RMS, XLR balanced output is 4V RMS
      DSD: RCA single-ended output is 1.8V RMS, XLR balanced output is 3.6V RMS
Output impedance: 22 ohms (RCA single ended) / 44 ohms (XLR balanced)
Frequency response: 20-20kHz +/-0.2dB
Signal to noise ratio: 125dB
Distortion characteristics:
      THD+N (1kHz, 0dBFS) 0.00025% at fs=44.1Khz (PCM)
      THD+N (1kHz, 0dBFS) 0.00030% at DSD256
Dynamic response (1kHz, -60dBFS) 125dB
Left and right channel separation >125dB

Balanced output noise floor: 2.2uv RMS

Amp balance maximum output power 3480mW@30Ω, 0dBFS
Load power
30Ω 3480mW
75Ω 1640mW
150Ω 920mW
300Ω 440mW
600Ω 220mW

Distortion of the amp balanced output, 0dBFS, fs=44.1Khz (PCM)
75Ω load THD+N -105dB
600Ω load THD+N -110dB

1, Windows 7, Windows 8, Windows 10; 32/64 bit, need to install a dedicated driver
2, Native MacOS 10.6 and later, using the system comes with a driver
3, Native Linux with UAC2 compliant kernel, using the system's own driver, (tested on Ubuntu and Daphile systems, based on X86 platform)
4, Android OS 4.2 and above, the device needs to support OTG function, in general, the Android 5.0 system is supported by default, and the following 5.0 recommendations are used with a dedicated player.

The I2S interface is input using an HDMI socket:

1. LVDS differential signal with a level of 3.3V;
2. The I2S interface is compatible with multiple I2S output signal definitions, and the FPGA has built-in PCM/DSD signal automatic identification algorithm;
3. The DSD ON signal can also be defined by itself. The DSD ON signal can be input to the PIN13, 14, 15, and 16 pins of the socket.
4. The phase of PIN1-3 and PIN7-9 is adjustable, and the user can configure the phase of the two pairs of outputs through one switch.

The SDA-2 can be configured with SW switches to accommodate different I2S standards.

Chassis size and packaging:

The length and width of the chassis: 262MM*220MM*46MM, excluding the height of the feet and the protruding part of the connector behind the chassis.
The weight of a single machine is about 3KG.
The length and width of the carton packaging: 330MM*310MM*110MM.
Shipping package weight: about 3.4KG
Accessories: a USB cable and a power cord